To realize high-speed, high-performance, low-power-consuming semiconductor devices, efforts have been made to increase the integration density of integrated circuits (ICs) by scaling down the sizes of transistors included in the ICs, while maintaining superior operating capabilities of the transistors. To increase the integration density of the ICs, the feature sizes of the semiconductor devices must be reduced.
Field effect transistors (FETs) used to increase the integration density of complementary MOS (CMOS) transistors include multi-gate transistors (for example, ‘35 nm CMOS FinFETs’, Symposium on VLSI Technology Digest of Technical Papers, pp. 104-105, 2002 by Fu-Liang Yang et al. and ‘High Performance Fully-Deleted Tri-Gate CMOS Transistors’, IEEE Electron Device Letters, Vol. 24, No. 4, April, 2003, pp. 263-365 by B. S. Doyle et al.). A multi-gate transistor includes a fin-shaped silicon body formed using a silicon-on-insulator (SOI) wafer and a gate formed on the surface of the fin-shaped silicon body.
The multi-gate transistor having the fin-shaped silicon body has a three-dimensional channel, which is useful for scaling the CMOS transistors. It is widely known that, with its fully depleted SOI structure, a multi-gate transistor offers superior sub-threshold characteristics and is capable of controlling electric currents without increasing the length of a gate. In addition, the multi-gate transistor does not suffer from a short channel effect (SCE) in which the potential of a channel region is affected by a drain voltage. In particular, a tri-gate CMOS transistor uses a channel formed around its three surfaces. Therefore, when designing an active region where a channel will be formed, a tri-gate CMOS transistor has greater margin for design in width and height of an active region than a FinFET.
FIG. 1A is a perspective view of a conventional multi-gate transistor. Referring to FIG. 1A, when manufacturing the multi-gate transistor, a silicon active region 12 serving as a source/drain is formed as mesa-type slabs on a buried oxide film 10. A channel passes through a portion of a gate line 14 covering a top surface and both sides of the silicon active region 12.
Electrical characteristics of the multi-gate transistor are greatly affected by the size (i.e., height and width) and the shape (i.e., a curvature or a rounding profile seen from above) of the silicon active region 12. In other words, non-uniform sizes and shapes of slabs of the silicon active region 12 covered by the gate line 14 may result in variations in the performance of the multi-gate transistor or degradation of its electrical characteristics.
FIG. 1B illustrates a reticle pattern in which an optical proximity correction (OPC) is applied when performing a lithography process for patterning an active region according to a conventional method of manufacturing a semiconductor device.
Referring to FIG. 1B, when patterning the silicon active region 12 shaped as illustrated in FIG. 1A, a reticle pattern including the OPC is used to prevent problems caused by a proximity effect of the lithography process. The recticle pattern includes slab patterns 22 of the silicon active region 12, and dummy patterns 24. In other words, in the prior art, each slab in the silicon active region 12 is independently patterned using the reticle pattern employing the OPC, and the slabs are connected to one another using lithography characteristics.
When performing the lithography process using the reticle pattern illustrated in FIG. 1B, an active region pattern 30 having a ‘rounding’ phenomenon is very likely to be formed as illustrated in FIG. 1C. FIG. 1C is a plan view of the silicon active region 12 formed using a multi-gate reticle including the OPC.
As the pitch of each of the slabs in the silicon active region 12 decreases, the slabs sustain more profile rounding and more CD (critical dimension) variations in a stage of after-development inspection (ADI) when forming the silicon active region 12 using the OPC as described with reference to FIG. 1B due to a resolution limitation of the lithography process. In particular, when forming a transistor in which a plurality of slabs extend parallel to one another, it is more difficult to pattern the active region to have a uniform profile and CD.